A MOSFET conducts on-off control of an electron flow or a hole flow between a source and a drain by changing the potential at a semiconductor (silicon) interface directly under a gate by a gate voltage.
However, when the channel length of the transistor is shortened, the space charge regions (also known as depletion layers) in the vicinity of the source and the drain come into contact with each other. At this time, the voltage of the semiconductor interface near the gate can be controlled by the gate voltage. However, even when the gate voltage is lowered, the voltage at the part of large depth from the gate stays high due to the influence of the drain voltage.
In other words, when the gate voltage is made 0 V to turn off the transistor, current flows through a part having a high potential (a part to which the space charge region spreads) in the semiconductor substrate. This is known as a short channel effect, which appears as a phenomena, such as an increase in S value (subthreshold coefficient) or a decrease in threshold voltage.
An example of a phenomenon largely contributed by the short channel effect is a punch through, in which current is kept flowing. The advantage of the miniaturization of a MOSFET is that it can be operated at a low voltage at a high speed. In order to succeed in realizing such miniaturization, suppression of the short channel effect and lowering of the resistance when the transistor is turned on become the important factors.
One example of a method for miniaturizing a MOSFET while suppressing the short channel effect is the scaling method developed by Dennard in 1974 which is well known. It is understood from this method that the following measures are effective to shorten the gate length while suppressing the short channel effect. (1) The gate is insulating film is made thin. (2) The source/drain junction depth is made small. (3) The width of the space charge region (depletion layer) is suppressed.
With respect to the item (1), the lower limit is 3 nm under present circumstances. With respect to the item (2), improvement of an ion doping apparatus and the use of laser doping have been investigated, but there still are various problems at a deep submicron size or less.
As for the method for the item (3), it is thought to increase the concentration of the channel forming region, i.e., channel doping. However, in order to produce a MOSFET with a fine dimension such as a wiring design rule of 0.18 μm, about 1×1018 atoms/cm3 of an impurity should be added, which becomes a factor of largely decreasing the on current.
The structure shown in FIG. 2 has been known to avoid such a phenomenon. In FIG. 2, numeral 201 denotes a source region, 202 denotes a drain region, 203 denotes an LDD region, and 204 denotes a gate electrode. An impurity region (punch through stopper) 205 having an opposite conductive type to the source/drain is formed under the gate electrode at a large depth. In this structure, the broadening of depletion layer from the drain side is suppressed by the punch through stopper 205 to prevent the short channel effect.
The formation of the punch through stopper 205 shown in FIG. 2 is accomplished by adding an impurity ion to the silicon substrate. At this time, the impurity ion to be added is added from the upper side of the silicon substrate, but some problems still exist.
The first problem is that when the impurity ion is added from the upper side of the silicon substrate, the crystallinity of the region at which the channel is formed, i.e., the crystallinity of the vicinity of the surface of the silicon substrate, is broken by the collision ions.
An improvement was recently conducted in that since the depth of the formation of the punch through stopper is small, the impurity ion is added at a small depth by lowering the acceleration voltage for addition of the ion or by adding a compound having a large mass number.
However, both of these methods lead to conditions that are liable to damage the silicon substrate. Further, it is expected that the disorder of the crystallinity in the vicinity of the surface of the silicon substrate becomes a severe problem with the miniaturization of the device. Such disorder of the crystallinity is not always completely recovered by an annealing treatment.
The second problem is that the impurity ion remains in the area where the channel is formed through the process of injecting the impurity ion into the silicon substrate.
The impurity ion added has a concentration distribution in the depth direction depending on the addition conditions. Therefore, when the addition conditions are set in such a manner that the peak value of the impurity concentration is arranged at the position at which the punch through stopper is formed, the tail part of the concentration profile is broadened toward the vicinity of the surface of the silicon substrate.
When the impurity ion is added from right above the silicon substrate, the tail part of the profile unavoidably remains at the vicinity of the surface of the silicon substrate. The impurity thus remains in the area where the channel is formed even at a lower value than the peak value.
The disorder of crystallinity and the presence of the impurity described above disturb the migration of the carrier, which results in various problems, such as lowering of the on current (the drain current when the FET is in an on state) and lowering of the mobility (field effect mobility).
As described in the foregoing, although the structure having the punch through stopper exhibits an effect on suppression of the short channel effect, it is expected that the problems of lowering of the on current and the mobility again arise with miniaturization.